Test Cases:
Testcases currently include the following designs.
- Ariane: We download the Ariane netlist from the lowRISC GitHub repository.
- 136 macro version: We instantiate 16-bit (256x16) memories to enable generation of the Ariane design with 136 macros.
- 133 macro version: The netlist of the 136-macro version is modified to generate the Ariane design with 133 macros. This is explained here.
- MemPool: The MemPool design is downloaded from the mempool GitHub repository.
- Tile: MemPool tile is part of MemPool which is an open-source many-core system.
- Group: MemPool Group is part of MemPool which contain 16 MemPool Tiles.
- NVDLA: The NVDLA design is downloaded from the nvdla/hw GitHub repository.
- NVDLA nv_small: We compile the RTL using the nv_small.spec available in the nvdla/hw GitHub repository. Only partition c has the memory macros, so we run all our flow only for partition c.
- BlackParrot: BlackParrot is a RISC-V multicore design. We provide the Verilog netlist of the BlackParrot Quad Core design.